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11. Instruction Scheduler

vsc - scheduler for vbcc (c) in 1997-99 by Volker Barthelmann

11.1 Introduction

vsc is an instruction-scheduler which reorders the assembly output of vbcc and tries to improve performance of the generated code by avoiding pipeline stalls etc.

Like the compiler vbcc it is split into a target independent and a target dependent part. However there may be code-generators for vbcc which do not have a corresponding scheduler.

This document only deals with the target independent parts of vsc. Be sure to read all the documents for your machine.

11.2 Usage

Usually vsc will be called by a frontend. However if you call it directly, it has to be done like this:

    vsc [options] input-file output-file

The following options are supported:


Do not print the copyright notice.


Set debug-level to <n>.

Note that depending on the target vbcc may insert hints into the generated code to tell vsc what CPU to schedule for. Code scheduled for a certain CPU may run much slower on slightly different CPUs. Therefore it is especially important to specify the correct target-CPU when compiling.

11.3 Known problems

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